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# Contents

* 1 Introduction
o 1.1 Motivation: IC Design Methodologies
o 1.2 Contents and Structure of this Manual
* 2 Basic VHDL Concepts
o 2.1 Components of a VHDL Model
o 2.2 Entity Declaration
o 2.3 Architecture
o 2.4 Configuration Declaration
o 2.5 Packages
o 2.6 Additional Signal Characteristics
o 2.7 Analysis of VHDL Models
o 2.8 Simulation
* 3 Data Types
o 3.1 Scalar Types
o 3.2 Composite Types
o 3.3 Access Types
o 3.4 File Types
o 3.5 Type and Field Attributes
* 4 Declarations and Identifiers
* 5 Expressions and Operators
* 6 Sequential Modeling
o 6.1 Assignments
o 6.2 Subprograms
* 7 Signals
o 7.1 Signal Declaration
o 7.2 Signal Assignments in Process
o 7.3 Implicit Type Resolution and Drivers
o 7.4 Signal Attributes
* 8 Concurrent Modeling
* 9 Structural Descriptions
o 9.1 Generation of Instances
o 9.2 Use of Packages
o 9.3 Configurations
o 9.4 Generics
* 10 Packages and Libraries

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