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*  Clock signal distribution is becoming ever more difficult. Even with fractal clock distribution schemes, the amount of power and circuit area required to keep all the chip moving in-step is prohibitive, and the amount of design effort to create such schemes is a significant fraction of the total design cycle.
* The power consumed by these circuits is consumed virtually entirely during the clock pulses. With clock frequencies approaching 1GHz, this means CPUs are a significant source of radio interference, and conventional designs can only rely on shielding to reduce this.
* Another problem is the sheer quantity of power consumed. This is particularly exacerbated by the way that all parts of the chip must be clocked simultaneously (in CMOS, power is only really ever consumed in state changes.) This can be reduced somewhat by clock-gating, but there are still large parts of a chip that are consuming power without doing any useful work. Because all parts of a chip must be clocked at the same frequency (or some multiple of it) a large part of the design effort must be put into making sure that all execution paths can reach a stable state within a clock cycle. This can be significantly difficult for exceptional paths (like illegal instruction traps) that are only very rarely taken (and might not ever occur in production systems.) Due to non-trivial clock distribution problems, it is often impractical to design circuit cells to work with variable widths of data buses, making design reuse much less frequent than it ought to be (comparing with the state of design reuse in software, for example.)

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